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IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCKTM JR.
FEATURES:
* * * * * * Eight zero delay outputs <250ps of output to output skew Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 15MHz to 85MHz 3 skew grades: IDT5V9910A-2: tSKEW0<250ps IDT5V9910A-5: tSKEW0<500ps IDT5V9910A-7: tSKEW0<750ps 3-level inputs for PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <200ps peak-to-peak Available in SOIC package
IDT5V9910A
DESCRIPTION:
The IDT5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
* * * * * *
FUNCTIONAL BLOCK DIAGRAM
VCCQ/PE GND/sOE Q0 Q1
Q2 Q3 PLL REF Q4 Q5 FS Q6 Q7
FB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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c 2001 Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC 5847/1
IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VI Description Supply Voltage to Ground DC Input Voltage REF Input Voltage Maximum Power Dissipation (TA = 85C) TSTG Storage Temperature Max -0.5 to +7 -0.5 to VCC+0.5 -0.5 to +5.5 530 -65 to +150 Unit V V V mW C
REF V CC Q FS NC VCCQ /P E VC C N Q0 Q1 G ND Q2 Q3 VC C N
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
G ND TE ST NC G ND/sO E V CCN Q7 Q6 G ND Q5 Q4 V CCN FB
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. 7 Unit pF
SOIC TOP VIEW
NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested.
PIN DESCRIPTION
Pin Name REF FB TEST (1) GND/ sOE(1) VCCQ/PE FS(2) Type IN IN IN IN IN IN Description Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Frequency range select: FS = GND: 15 to 35MHz FS = MID (or open): 25 to 60MHz FS = VCC: 40 to 85MHz Q0 - Q7 VCCN VCCQ GND OUT PWR PWR PWR Eight clock output Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground
NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
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IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
IDT5V9910A-5, -7 (Industrial) Symbol VCC TA Description Power Supply Voltage Ambient Operating Temperature Min. 3 -40 Max. 3.6 +85 3 0 IDT5V9910A-2 (Commercial) Min. Max. 3.6 +70 Unit V C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage(1) Input MID Voltage(1) Input LOW Voltage(1) Input Leakage Current (REF, FB Inputs Only) I3 IPU IPD VOH VOL 3-Level Input DC Current (TEST, FS) Input Pull-Up Current (VCCQ/PE) Input Pull-Down Current (GND/sOE) Output HIGH Voltage Output LOW Voltage Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VCC or GND VCC = Max. VIN = VCC VIN = VCC/2 VIN = GND VCC = Max., VIN = GND VCC = Max., VIN = VCC VCC = Min., IOH = -12mA VCC = Min., IOL = 12mA HIGH Level MID Level LOW Level -- -- -- -- -- 2.4 -- 200 50 200 100 100 -- 0.55 A A V V A Min. 2 -- VCC-0.6 VCC/2-0.3 -- -- Max. -- 0.8 -- VCC/2+0.3 0.6 5 Unit V V V V V A
NOTE: 1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol ICCQ ICC ICCD ITOT Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Total Power Supply Current Test Conditions(1) VCC = Max., TEST = MID, REF = LOW, GND/sOE = LOW, All outputs unloaded VCC = Max., VIN = 3V VCC = Max., CL = 0pF VCC = 3.3V, FREF = 25MHz, CL = 160pF(1) VCC = 3.3V, FREF = 33MHz, CL = 160pF(1) VCC = 3.3V, FREF = 66MHz,
NOTE: 1. For eight outputs, each loaded with 20pF.
Typ.(2) 8 1 55 34 42 76
Max. 25 30 90 -- -- --
Unit mA A A/MHz mA
CL = 160pF(1)
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IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol tR, tF tPWC DH REF Description (1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle Reference clock input Min. -- 3 10 15 Max. 10 -- 90 85 Unit ns/V ns % MHz
NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5V9910A-2 Symbol Parameter FS = LOW FREF tRPWH tRPWL tSKEW0 tDEV tPD tODCV tORISE tOFALL tLOCK tJR REF Frequency Range REF Pulse Width HIGH
(8)
IDT5V9910A-5 Max. 35 60 85 -- -- 0.25 0.75 0.25 1.2 1.2 1.2 0.5 25 200 Min. 15 25 40 3 3 -- -- Typ. -- -- -- -- -- 0.25 -- 0 0 1 1 -- -- -- Max. 35 60 85 -- -- 0.5 1.25 0.5 1.2 1.5 1.5 0.5 25 200 15 25 40 3 3 -- --
IDT5V9910A-7 Min. Typ. -- -- -- -- -- 0.3 -- 0 0 1.5 1.5 -- -- -- Max. 35 60 85 -- -- 0.75 1.65 0.7 1.2 2.5 2.5 0.5 25 200 ns ns ns ns ns ns ns ns ms ps MHz Unit
Min. 15 25 40 3 3
(1,3,4)
Typ. -- -- -- -- -- 0.1 -- 0 0 1 1 -- -- --
FS = MED FS = HIGH
REF Pulse Width LOW(8) Zero Output Skew (All Outputs) Device-to-Device Skew(1,2,5) REF Input to FB Propagation Delay(1,7) Output Duty Cycle Variation from 50% Output Rise Time(1) Output Fall Time(1) PLL Lock Time(1,6) Cycle-to-Cycle Output Jitter(1) RMS Peak-to-Peak
(1)
-- --
-0.25 -1.2
0.15 0.15 -- -- --
-0.5 -1.2
0.15 0.15 -- -- --
-0.7 -1.2
0.15 0.15 -- -- --
NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outlets. See AC TEST LOADS. 4. For IDT5V9910A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max. 5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns. 8. Refer to INPUT TIMING REQUIREMENTS for more detail.
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IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
1ns 1ns
VCC
3.0V 2.0V Vth = 1.5V
150 Outpu t
0.8V 0V
LVTTL Input Test Waveform
150 20p F
tOR ISE
tOF AL L
Test Load
2.0V
0.8V
LVTTL Output Waveform
AC TIMING DIAGRAM
tREF tRPW H REF tRPWL
tPD
tODCV
tODCV
FB
tJR Q
tSKEW
tSKEW
OTHER Q
NOTES: Skew: tSKEW: tDEV: tODCV: tLOCK:
The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75 to VCC/2. The skew between all outputs. The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
tORISE and tOFALL are measured between 0.8V and 2V.
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IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
ID T XXXXX XX Package X Process Device Type
Blank I
Commercial (0C to +70C) Industrial (-40C to +85C)
SO
Small Outline IC (300-mil)
5V9910A-2 5V9910A-5 5V9910A-7
3.3V Low Skew PLL Clock Driver TurboC lock Jr.
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for Tech Support: logichelp@idt.com (408) 654-6459
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